PIC16F639-E/SS【PDF 36/74 页】IC MCU FLASH 2KX14 20SSOP

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Sheet目录3876

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Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

Bit

Default

Read/

Write

Description

DMRPSIE DMA MAC Receive Process Stopped Interrupt Enable

When this bit is set, the DMA MAC Receive Process Stopped Interrupt

is enabled.

When this bit is reset, the DMA MAC Receive Process Stopped

Interrupt is disabled.

24 - 0

Reserved

Interrupt Status Register (INTST Offset 0x002C)

This register contains all the status bits for the ARM CPU. When corresponding enable bit is set, it cause the CPU to be

interrupted. This register is usually read by the driver during interrupt service routine or polling. The register bits are not

cleared when read. Each field can be masked.

The following table shows the register bit fields.

Bit

Default

Read/

Write

Description

DMLCS DMA MAC Link Changed Status

When this bit is set, it indicates that the DMA MAC link status has

changed from link up to link down or from link down to link up.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

DMTS DMA MAC Transmit Status

When this bit is set, it indicates that the DMA MAC has transmitted at

least a frame on the DMA port and the MAC is ready for new frames

from the host.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

DMRS DMA MAC Receive Status

When this bit is set, it indicates that the DMA MAC has received a

frame from the DMA port and it is ready for the host to process

This edge-triggered interrupt status is cleared by writing 1 to this bit.

DMTBUS DMA MAC Transmit Buffer Unavailable Status

When this bit is set, it indicates that the next descriptor on the transmit

list is owned by the host and cannot be acquired by the KSZ8841-

PMQL. The transmission process is suspended. To resume processing

transmit descriptors, the host should change the ownership bit of the

descriptor and then issue a transmit start command.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

DMRBUS DMA MAC Receive Buffer Unavailable Status

When this bit is set, it indicates that the descriptor list is owned by the

host and cannot be acquired by the KSZ8841-PMQL. The receiving

process is suspended. To resume processing receive descriptors, the

host should change the ownership of the descriptor and may issue a

receive start command. If no receive start command is issued, the

receiving process resumes when the next recognized incoming frame is

received. After the first assertion, this bit is not asserted for any

subsequent not owned receive descriptors fetches. This bit is asserted

only when the previous receive descriptor was owned by the KSZ8841-

PMQL.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

DMTPSS DMA MAC Transmit Process Stopped Status

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